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Altera_Forum's avatar
Altera_Forum
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14 years ago

Question about 2x clocking

Hi All, I have a question about clocking. I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work. I have no idea why it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can try

always @ (posedge clkB)

dataH <= data_A;

always @ (nedged clkB)

dataL <= data_B;

data <= clkB = 1'b1 ? dataH : dataL;

However, if you want to synthetize this, it's best to use a ALTDDR block.