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When an SoC design generated by Qsys is compiled in quartus there are a bunch of warnings generated. In the training classes they always tell us to ignore these warnings. In general, I like to know the cause of each warning before I decide to ignore it. That said, I came across a set of warnings today in my own design that I do not see when I compile the example design from the training class:
Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File .../hps_AC_ROM.hex -- setting all initial values to 0
Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File .../hps_inst_ROM.hex -- setting all initial values to 0
My design only instantiates the hps and nothing else. Also I compiled the example design from the training class using 13.0 and my design using 13.0sp1. I don't think this is the difference, but maybe it is?
I appreciate any insight. Thanks.
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Help:
http://quartushelp.altera.com/13.0/mergedprojects/msgs/msgs.htm#msgs/wcdb_cdb_file_not_found.htm Just skip this critical warning message.
ZS.V.
Honored Contributor
