Quartus Prime Lite - Difficulties with simulation

Thanks very much for taking the time to verify that it doesn't work! It would have been simple to have left it without trying the 10 LP and ALTPLL, and I would have spent a bunch of time fruitlessly trying to replicate your results in my environment. I'm glad to know that I'm not (completely) crazy or a (complete) moron. :)

Any suggestions for tricking a testbench into generating the PLL output clock without changing the synthesized code? I suppose I could just create a version with an input clock to the FPGA that replaces the PLL output for functional testing, but the timing would likely be totally whacked.

And please advise on the estimated timeframe for the simulator fix. I know that's asking a lot.

Thanks again!