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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus II compilation error message for pll clock fan out

Hi, I'm working on a design. After compilation, I got a message as below. Error: Net "enet_refclk_125MHz", which fans out to "test_clk_1", cannot be assigned more than one value Error:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi msj,

Thanks for your answer. After receiving your comment, I've tried to check my code,

there was an error that I connected enet_refclk_125MHz to an output port of anther

module too. The message was misleading me to a problem of the clock fan outs.

It is solved now.

Thank you!

Peter Chang