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Altera_Forum's avatar
Altera_Forum
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9 years ago

Quartus II compilation error message for pll clock fan out

Hi, I'm working on a design. After compilation, I got a message as below. Error: Net "enet_refclk_125MHz", which fans out to "test_clk_1", cannot be assigned more than one value Error:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It seems that you have fed your clock from two different sources. Feed it by one source or use a clock control core for supplying it with several clocks.