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Altera_Forum
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14 years ago

Qsys SDRAM wire export, clk missing

Hi All, This is a newbie question. I don’t have much luck adding SDRAM to my project. I’ve completed the “Nios II Hardware Development Tutorial” and the first count binary demo is worki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Are you sure you parameterized the memory controller the same way as before? Qsys is just exporting the wires/buses it sees coming from the SDRAM controller so if you have a mismatch that effects the addressing I would expect the behavior you are seeing.