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Honored Contributor
Honored ContributorQsys SDRAM wire export, clk missing
Hi All, This is a newbie question. I don’t have much luck adding SDRAM to my project. I’ve completed the “Nios II Hardware Development Tutorial” and the first count binary demo is worki...
Altera_ForumHonored Contributor
Honored ContributorAre you sure you parameterized the memory controller the same way as before? Qsys is just exporting the wires/buses it sees coming from the SDRAM controller so if you have a mismatch that effects the addressing I would expect the behavior you are seeing.
