Qsys SDRAM wire export, clk missing

I don't know anything about that board but you most likely need to either create another PLL output for the SDRAM and export it or add a clock bridge component (under merlin components), wire up the c1 port of the PLL to the bridge input and export the output. Creating another PLL output is probably the easier way to do this especially if you plan on putting a phase shift on that exported clock.