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Altera_Forum
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14 years ago

Qsys SDRAM wire export, clk missing

Hi All, This is a newbie question. I don’t have much luck adding SDRAM to my project. I’ve completed the “Nios II Hardware Development Tutorial” and the first count binary demo is worki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I don't know anything about that board but you most likely need to either create another PLL output for the SDRAM and export it or add a clock bridge component (under merlin components), wire up the c1 port of the PLL to the bridge input and export the output. Creating another PLL output is probably the easier way to do this especially if you plan on putting a phase shift on that exported clock.