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Altera_Forum
Honored Contributor
15 years agoQsys poor fmax peformance
Hi, I just want to know if somebody has experienced the same issue. I took an old SOPC Bulider design, compiled with Q8.1 for a EP3C25F256C8 device and used Q11 to convert it to Qsys. As SOPC b...
Altera_Forum
Honored Contributor
15 years ago@BadOmen : The system is a very common system with 10 masters and approx. 10 slaves. The resource usage in the EP3C25 is about 62% of LE's and 97% of M9K. As I already mentioned, this is an old SOPC Builder system, which is converted to Qsys. I took the same timing constraints for the Qsys design. The design is properly constraint. With SOPC builder 75 Mhz is not a problem, with Qsys and no pipeline stages Fmax is about 64 MHz. This is only 85% of the fmax performance of the SOPC Bullder design. The top failing path is a NIOS path. It's from IEM:inst|IEM_cpu:cpu|d_read to IEM:inst|altera_merlin_master_translator:cpu_data_master_translator|address_register[24]
with a total delay of 15.566 ns.