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Altera_Forum
Honored Contributor
Honored ContributorQsys error:While creating NEW IP
Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Image is not clear can you reattach the screen short of the error and interconnect in two image? Regards Anand
