Qsys Avalon ST Conduits

Question

Hi Guys,

I'm frustratingly working my way through the SOPC webinars and documents on SOPC and avalon.

(If your interested i'm trying to learn this so i can make a video output stream from HDL onto the avalon and out a TSE_MAC)

my problem is conduits. when i turn an avalonst sink into a conduit, it duplicates my conduit and the reset signal when i finish the component. whats the go?! Why, and what are they for? Am i doing something wrong?

Thanks in advance

-------------------------------------------------

fyi my steps

I start a new component in Qsys.
Use templates menu and select Avalon ST Sink.
It makes the signals and interfaces.
Either by the signals tab or interfaces tab I add a new conduit interface.
Convert the AvST-Sink interface signals to the new conduit.
Use the "remove unused interfaces button"
Look at the GUI. All is well. Just has the clk, reset and my single conduit line.
Press finish.

Then it decides to insert an extra conduit and reset. WTF?!

See pic, the red are the extra ones.

--------------------------------------------------------------

altera_forum · Answer

Let me explain what I have understood about conduits. I think the conduits that you are talking about was also there in SOPC but you were not able to see them. Use the conduits only if you want your signals to go out of the Qsys system [to either another Qsys system or outside the FPGA].

In Qsys all conduits well be associated with a reset. [I haven't found a way to get rid of these]

What does your this component do, I may be able to tell you how to handle the conduits in your case.

altera_forum · Answer

Thanks for the reply.

I'm using conduits as a connection from my Verilog HDL to the SOPC system.

What i want to do is send a constant stream of pixel data to be prepared as packets for passing to the Tripple Speed Ethernet MAC (via a multiplexor).

I've managed to make the double up conduits go away on my example, by explicitly writing some HDL for the component and using that as its base in the editor.

But things i'm still trying to understand (doing alot of reading atm).

streaming and data widths and symbol size:
I can't quite understand how the stream works
- What does the symbol size define? It can't be depth because that would be infinite yeah?
packet creation: Ideally i would want to create the packets in HDL, but there is a limit of 1024 width. So you can't do a packet a cycle. I still need to understand it more before i can figure this i suppose.

Any suggestions of research paths or methods would be greatly appreciated.

altera_forum · Answer

Are you using SOPC builder or Qsys builder ?

altera_forum · Answer

I'm using QSys now

altera_forum · Answer

Symbols are units of data (just like bytes are units of data for MM). Here is some terminology:

Symbol --> unit of data

ST data width --> total width of the data port (containing one or more symbols per beat)

Beat --> transfer of data from ST source to ST sink

So if you had a 32-bit ST port containing two 16-bit symbols you would declare the ST port as having two symbols per beat.

A packet is typically formed of one or more beats and not just a really wide ST source/sink. As you send the packet you signal the start of the packet by asserting the start of packet signal and on the last beat you assert the end of packet signal. So unless I'm missing something here I think what you want to do is expose a streaming port and send one or more symbols per beat to the exported port.

Forum Discussion

Qsys Avalon ST Conduits

7 Replies

Recent Discussions

Max10 Security Bit

Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?

MAX 10. No 3.0 V Schmitt Trigger I/O standard

Agilex Reset_Release no associated clock

Agilex5 Engineering Silicon