Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Qsys - Add rx buffer/FIFO for SPI slave block - (CYCLONII:EP2C8F256C7)

Hello,I would like to know is there any way/solution to add FIFO/buffer SPI rx data. Today, there is only register - 'RXDATA' is overridden every time. Thanks, Arthur.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Are you hoping for a FIFO implemented in hardware or software?

The IP doesn't have an option to add a FIFO. However, it could be possible to add an external hardware (rtl) FIFO, to operate alongside the IP.

Having said that, I'd have thought that a FIFO, implemented in software, is the recognised way to do this - assuming you're implementing a Nios core in your solution. Use the RRDY interrupt to trigger your interrupt routine and buffer the RXDATA.

Cheers,

Alex