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Honored Contributor
Honored Contributorpuzzled by the chapter of "LVDS Interface with the Use External PLL Option Enabled"
I am reading stx4_siv51008.pdf. I am puzzled by the chapter of "LVDS Interface with the Use External PLL Option Enabled". they discussed 3 signal "Serial clock ,Load enable , Parallel clock" whi...
Altera_ForumHonored Contributor
Honored ContributorFitter Report -> PLL Usage, tells what each output does. You need to then correlate that back to the one you create.
