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Altera_Forum
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12 years ago

processes: while loop does not work, for loop does work. Why?

I want to write this code for a basic synchronous counter more efficiently... u_count: process(rst_i, clk_i) -- generated on rising edge variable i: integer :=1; begin if rst_i = '1' ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Why not post that example? Afaik, it is able to process it if you put an exit staement in the code. Also, a point to note, you did not post your whole code (just a snippet). Why not post the real code.

The Altera VHDL compiler is actually one of the better VHDL synthesisors out there.

The VHDL compiler HAS to convert to logic in Quartus. it has specific templates to follow and is actually pretty good at converting to logic. Post this example your on about, and we'll see if it really is a logic example.