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Altera_Forum
Honored Contributor
14 years agoOk it's a QSys bug. You need to fix the Qsys generated topfile and insert output [0:0] wire in odt, cse and ckn signals
Ok it's a QSys bug. You need to fix the Qsys generated topfile and insert output [0:0] wire in odt, cse and ckn signals