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Altera_Forum
Honored Contributor
Honored Contributorproblems on my thesis
Heyy I'm doing my thesis on tetris game simulation on fpga and not good at vhdl that much. Your asist would be great. At first, i need to make the code below work. It's just the beginning of VGA code...
Altera_ForumHonored Contributor
Honored ContributorI think the main problem is that you are dividing your clock by two to generate a logic clock. This is generally a bad thing to do. You should clock everything from the main clock and then produce clock enables when everything needs to change.
