Problems about DDR2!

Hello,

the output enable group entry is important. When you use e. g. the Quartus DDR2 "High Performance Controller" reference design, this option is automaticly set from tcl script ddr2_pin_assignments.tcl together with IO standards.

But it could be, that your design flow is different from Altera predestinated way. Then you get the said errors, possibly wondering if your design would be operational at all.

Unfortunately, the output enable group option is neither mentioned anywhere in DDR2 controller user guides, nor in device handbooks where SSO constraints are discussed.

Only Quartus software handbook has an appropriate description:

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For interfaces that use bidirectional VREF I/O pins, the VREF restriction must be met when the pins are driving in either direction. If a set of bidirectional signals are controlled by different output enables, the I/O Assignment Analysis command treats these as independent output enables. Use the output enable group logic option assignment to treat the set of bidirectional signals as a single output enable. This is important in the case of external memory interfaces. (A full page of examples follows)

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Regards,

Frank