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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with port mapping in Quartus

Hello, I am trying to model a two dimensional array of registers using port mapping in quartus. I have first designed a five stage shift register for which I am getting the desired result i.e., th...
Altera_Forum's avatar
Altera_Forum
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13 years ago

so another weird issue... (not even sure if you check these forums anymore but whatever)... You are using a structural way to define components but call the architecture type 'Behavioral' (architecture behavioral of memoryblock is).. This might be throwing you off.

Your original shift register is indeed behavioral as it uses a process that sequentially executes.

If you are trying to use that behavioral inside a structural, maybe that's a problem.. I wouldn't know since I'm a noob to VHDL but just looking at your naming convention does seem to be confusing and perhaps there is something you are overlooking between the two different ways to generate your logic.

~doddy