Problem with FIR II core

Hi Kaz,

I don't understand what you mean by "path". Probably we still misunderstood.

Let me try again:

1. I have single 16 bit, 288Hz data stream (you can think it represents one analog signal acquired with 16bit ADC, clocked with 288MHz)

2. I want to filter this signal (in digital domain) using symmetrical FIR with 11 coefficients

3. My current system is implement such a way that I get four 16 bit samples from the stream at once. (This means that I get 4 samples each 72 MHz)

How would you approach this problem in Quartus ?

In my current system I have access to 72MHz clock. I don't have 288mhz but probably I can use PLL to make it.

I would prefer I solve this using FIR II core clocked at 72MHz, if possible? (even for the sake of 4 times more hardware)

But if this is the only option I will try to go with 288Mhz clock.

Is my question more clear now?

Regards

Dimitar