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Altera_Forum
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15 years ago

problem with cyclone POR

Hi! I'm using Cyclone I fpga. During reset my IO pins are not stable...their vibrating between '0' to tristate.. Is this normal? if so, I need a solution to keep my IO pins on tristate. can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think, the relation between configuration phase and reset behaviour in the original post is misleading. It's rather a pure reset problem, that's completely located in the NIOS software or possibly FPGA code.

Achieving a clean synchronous reset deassertion is an important point, but I guess, it's implemented for the NIOS core anyway.

Using SignalTap to trace the problem woud be next step, if no obvious reason can bedetected. There's a SignalTap option to use a reset trigger for data aquisition.