Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

problem with cyclone POR

Hi! I'm using Cyclone I fpga. During reset my IO pins are not stable...their vibrating between '0' to tristate.. Is this normal? if so, I need a solution to keep my IO pins on tristate. can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Dave and thanks again!

I'm Using an Peripherial output of NIOS PROCESSOR, I'v looked at the signal with an agillent scope. I can see the glitches you were talked about.

about the reset, I didn't quite understand... my reset is a hardwere reset, I cant control it from Quartus...so what you meant is to put an actuall DFF between the reset circuit to the altera's reset input, and synchronize it to the clock?

and also... I dont have enought logic elements to map the signals to Signal Tap.

and how can I enable a weak pull-up resistor to the output?