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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with cyclone POR

Hi! I'm using Cyclone I fpga. During reset my IO pins are not stable...their vibrating between '0' to tristate.. Is this normal? if so, I need a solution to keep my IO pins on tristate. can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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During reset my IO pins are not stable...their vibrating between '0' to tristate..

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Are the pins that are 'unstable' clocked, and how is the reset signal generated, and then conditioned? For example, an external reset signal should be 'clean', no glitches, and should be synchronized to the clock domain in which it is used using a cascaded DFF (there are recommendations on the Altera web site). This results in asynchronous reset assertion and synchronous deassertion.

Cheers,

Dave