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Altera_Forum
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15 years ago

problem with cyclone POR

Hi! I'm using Cyclone I fpga. During reset my IO pins are not stable...their vibrating between '0' to tristate.. Is this normal? if so, I need a solution to keep my IO pins on tristate. can ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi mackrants,

--- Quote Start ---

the current pin is an output from my NIOS processor.

I dont think I can make logic errors when sellecting an IO pin in a processor :)

Do you have any suggestions?

--- Quote End ---

Can you describe the problem a little better please. For example, is the output a signal from a PIO component on the Avalon bus or is it a direct processor pin (which one)? Or some other signal? What are you trying to control with the I/O, have you enabled a weak pull-up on the signal?

What are you using to look at the signal to determine that it is going between 0 and tri-state? Have you used SignalTap II to capture a trace of the signal?

Cheers,

Dave