Problem using VHDL from a project lower in the heirarchy in an upper level

I was hoping someone had seen a similar problem so I wouldn't have to get into too great a detail, but here goes. When I received the original error, I found the following lines in the VHDL generated by the Altera Megafunction for LPM_DFF--

-- use the following when compiling in Quartus II

--LIBRARY lpm;

--USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --

-- add lpm_pack.vhd from the Quartus II library

LIBRARY work;

USE work.lpm_components.all;

I commented out the work one and uncommented the LPM one as follows--

-- use the following when compiling in Quartus II

LIBRARY lpm;

USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --

-- add lpm_pack.vhd from the Quartus II library

--LIBRARY work;

--USE work.lpm_components.all;

This led me to this error---

Error (10482): VHDL error at lpm_dff_0.vhd(44): object "lpm_dff" is used but not declared

When I commented out the _0 lines and changed them to take off the _0 as in the following VHDL---

-- PROGRAM "Quartus II 32-bit"

-- VERSION "Version 12.1 Build 177 11/07/2012 SJ Web Edition"

-- CREATED "Thu Jan 17 23:22:14 2013"

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-- use the following when compiling in Quartus II

LIBRARY lpm;

USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --

-- add lpm_pack.vhd from the Quartus II library

--LIBRARY work;

--USE work.lpm_components.all;

--ENTITY lpm_dff_0 IS

ENTITY lpm_dff IS

PORT

(

clock : IN STD_LOGIC;

data : IN STD_LOGIC_VECTOR(0 TO 0);

q : OUT STD_LOGIC_VECTOR(0 TO 0)

);

--END lpm_dff_0;

END lpm_dff;

--ARCHITECTURE bdf_type OF lpm_dff_0 IS

ARCHITECTURE bdf_type OF lpm_dff IS

BEGIN

-- instantiate LPM macrofunction

b2v_inst : lpm_dff

GENERIC MAP(LPM_WIDTH => 1)

PORT MAP(clock => clock,

data => data,

q => q);

END bdf_type;

I got the following error--

Error (10349): VHDL Association List error at lpm_dff_0.vhd(48): formal "LPM_WIDTH" does not exist

Since this indicates the key paramter LPM_WIDTH is not there in substantiated VHDL, I sent out this cry for help.

What doesn't make sense to me is why Quartus would generate VHDL that is not usuable in Quartus!!

Does anyone have any ideas keeping in mind that I am not generating the VHDL in question but it is being generated by Quartus.

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Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished?

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Its not Quartus, its a requirement of the VHDL language ...

-- Altera LPM components
library lpm;
use lpm.lpm_components.all;

Cheers,

Dave