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Wow - that TCL script is pretty handy and worked first time! Really impressive!
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I'm glad it made your learning easier :)
If you ever need to figure out what Tcl command to use relative to a Quartus GUI setting, you can create a Tcl file from the current project settings via Project->Generate Tcl file for Project.
In fact, I recommend doing that with the 'basic' project you just synthesized, then compare that single Tcl script to the constraints.tcl and synth.tcl scripts, and you'll be able to see how the Tcl is separated into common code in constraints.tcl and project-specific code in synth.tcl. The format of the pin constraints in constraints.tcl is made more compact using Tcl lists for the assignments that belong to one pin. This format was inspired by the Xilinx UCF format, since its less verbose than the Altera format.
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Ok, I've sucessfully downloaded your basic program into my nano, and it works well. There was a single curious item: my first attempt (Start...) failed.
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I've noticed this under Windows 7. My guess is that the Altera JTAG server and driver interface is screwy.
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I tried the other modes, of which only passive serial was available, and it failed as well. I then tried JTAG again, and it programmed immediately; the LED counter ran as expected.
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The USB-Blaster is essentially a USB to digital I/O controller. It can communicate to the JTAG header on an FPGA board, or the Active Serial header on an FPGA board. The USB-Blaster hard-wired on your DE0-nano can only speak JTAG-mode, so that is the only appropriate mode to use.
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I've reviewed the code, and as you mentioned, it is pretty rudimentary but very easy to comprehend. What I'll continue to review this morning is your SDC file and how to define the pins assignment/layout (something that I'm not yet familiar with). (It is obvious that I need to add TCL to my programming languages. I've noticed that it is the programming language in Quartus, so it makes sense to learn it as well.)
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Ask questions, and I'll answer them.
Altera, Xilinx, Lattice, and Mentor's tools can all be scripted with Tcl, so its worth learning.
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Oh, one other short note: I'm not really new to FPGA devices and programming. My first design (a pair of Xilinx FPGAs) was done in the late '80s and a second design (can't remember if it was one or two Xilinx devices) was done in the early '90s. Of course, the tools have improved dramatically since then! I'm simply trying to catch up on the new stuff ala Altera.
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They've added lots more features to FPGAs since then; DSP blocks, PLLs, memory, ARM cores, etc. The data sheets have got a lot longer!!!
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Thanks so much for the work that you put into these samples/templates! They both are very useful to me now. If you are ever in Plano, TX, I owe you lunch!
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Mmmm, Texas barbeque ... sounds tasty :)
Cheers,
Dave
Honored Contributor
