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Altera_Forum
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18 years ago

PLL-Phase relationship

Hi, does anybody know how to keep the phase relationship with respect to the input clock? The input clock for the PLL2 is the output clock from PLL1. Following the PLL2 settings: Input cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The input clock for PLL2 isn't ready before FPGA power-up. Only the input clock for PLL1, which output generates the PLL2 input clock, is ready before FPGA power-up.

I tried to reset (areset) the PLL2 after the PLL1 is locked but I still have different phases between input and output clock.