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Altera_Forum
Honored Contributor
Honored ContributorPLL-Phase relationship
Hi, does anybody know how to keep the phase relationship with respect to the input clock? The input clock for the PLL2 is the output clock from PLL1. Following the PLL2 settings: Input cl...
Altera_ForumHonored Contributor
Honored ContributorIf the input clock is present before FPGA power up, the PLL output should have a defined phase with PLL standard settings, to my opinion. If the PLL looses lock afterwards, respectively the input clock isn't present in time, the phase is undefined and a PLL reset necessary to reset it to defined conditions.
