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Altera_Forum
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14 years ago

PLL frequency lock range

Hi, I have a serial video signal that I want to take into an FPGA, with a parallel clock that could range from about 20MHz up to 150MHz. I'm using an Arria II GX. Am I able to get the PLL in th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If what you need is a division and not a multiplication, then no PLL is needed. You can use a clock enable system instead. Put your parallel clock as the FIFO write clock, and only enable the FIFO's write signals on the clock cycles that have valid data on.