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Honored Contributor
Honored ContributorPLL frequency lock range
Hi, I have a serial video signal that I want to take into an FPGA, with a parallel clock that could range from about 20MHz up to 150MHz. I'm using an Arria II GX. Am I able to get the PLL in th...
Altera_ForumHonored Contributor
Honored ContributorHi,
I need to divide the parallel clock's period in order to sample the high speed serial signal. I thought I needed a PLL for that. Is there another way, using a dual clock fifo in the design? Cheers Alex
