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Honored Contributor
Honored ContributorPLL frequency lock range
Hi, I have a serial video signal that I want to take into an FPGA, with a parallel clock that could range from about 20MHz up to 150MHz. I'm using an Arria II GX. Am I able to get the PLL in th...
Altera_ForumHonored Contributor
Honored ContributorAlex,
The easiest way to handle this is to feed the data and clock into dual clock fifo. This allows the input data/clock to vary to any value. Then you can process with a fixed clock on the other side. No changes in the PLL input frequency.
