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Altera_Forum
Honored Contributor
Honored ContributorPLL clock output
Hi, My design needs the PLL-clock output to be mapped to non-dedicated clock output pin of FPGA. When I do so, the following error message appears. What would be the best solution? War...
Altera_ForumHonored Contributor
Honored ContributorThere's a clock control megafunction ALTCLKCTRL: http://www.altera.com/literature/ug/ug_altclock.pdf.
PLL's outputs are already connected to global clock networks, so you don't need to implement any additional buffers.
