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Altera_Forum's avatar
Altera_Forum
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15 years ago

PLL clock output

Hi, My design needs the PLL-clock output to be mapped to non-dedicated clock output pin of FPGA. When I do so, the following error message appears. What would be the best solution? War...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yeah, It was warning message only. Is there any option like inserting clock buffers as in Xilinx ??!!!