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Altera_Forum
Honored Contributor
18 years agoPLL CLK OUTPUT I/Os
I'm using one PLL on my Cyclone III device to generate two CLKs with a 50MHz oscillator as input. From the literature it seems that CLK output c0 can be fed directly to one of the PLL CLKOUT pins. My...
Altera_Forum
Honored Contributor
18 years agoWith Cyclone III, you have the option to clock the second PLL from the same input (or to chain PLLs). This option involves additional clock uncertainty and jitter, as when using a non-dedicated clock output. But both variants are probably sufficient for many applications.
For maximum clock performance, both PLLs should be clocked directly from an external distribution buffer, preferably with a differential I/O standard.