Pin Assignment doubt

Question

Hello,

I have assigned "addr_from_the_ixp465_rwdata_0[0]" to the pin PIN_AB10 in the pin planner. I get the following line in the .qsf file.

set_location_assignment pin_ab10 -to addr_from_the_ixp465_rwdata_0[0]. Is there any other way to do this? Manually typing each and every pin name is time consuming.

Later I tried assigning the whole node to the IOBANK and I got the following sentence in the .qsf file.

set_location_assignment iobank_3 -to writedata_from_the_ixp465_rwdata_0. Have I successfully assigned the nodes to the pins in the above statement[since I don't see the pin name I am doubtful]?

Also How do I make the pins assignment virtual.

Thanks,

AA

altera_forum · Answer

the pins have to be assigned individually. You are much better off using the default assignment .qsf off of altera's website (that way you don't have to type everything out) and use the names already given. This also makes life a lot easier if you ever need to switch boards.

altera_forum · Answer

The quickest way is to drag and drop in the pin planner. You can grab multiple nodes or and busses.

The ports allow a special nomenclature whereby the bus is grabbed even if the index isn't listed. I try to use wildcards though for assignments that allow them. The Assignment Editor pull-down menu should have an (allows wildcards) by assignments that allow them, but I have seen assignments except them even thought it didn't explicitly say so.

The Assignment Editor is the best place to make virtual pin assignments. Click in the empty To column and on the right side a little menu will access the Node Finder. Change the filter to Pins: All, and then search away. Grab all the ones you want and then make the assignment. I recommend against making clocks(and maybe resets) into virtual pins, as they get put into the general routing fabric.

altera_forum · Answer

Hello Rysc,

I dragged and dropped the entire bus[24 signals] to the pins into the IOBANK [is this what you are telling me to do?] In the resources window I can see the that the pins are being used. but when I compile my design I still get the warning " Critical Warning: No exact pin location assignment(s) for 94 pins of 94 total pins". Why is this happening?

Thanks,

AA

altera_forum · Answer

I assume it doesn't consider an IO bank to be an exact pin location.  For anything going into a real board, it's imperative that every I/O has an exact pin location(to a specific pin, not just a bank) or it won't work.  Hence the critical warning.  If you're not going to a board, then it's fine and you can ignore the warning.

altera_forum · Answer

I could find only two places where I could drag and drop my bus.

a. In the IO bank

b. When I switch to the "top view - WIre Bond" I can drag and drop the bus to the EDGE_LEFT, EDGE_TOP,EDGE_RIGHT,EDGE_BOTTOM. [Is this what you are talking about]

Forum Discussion

Pin Assignment doubt

8 Replies

Recent Discussions

Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL?

LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve

Cyclone 10LP 3.3V interface 3.0V VCCIO Bank

MAX10 Soft SERDES set_input_delay constraints

Potential Documentation Error in ES-1057 Errata Doc: "HPS EMAC" Issue Listed for Arria 10 GX/GT