PFL with S4 and MAXii

Hi!

Glad to hear that you made it and sorry for my late reply.

I was about to send you my design and schematics as well.

Admittedly, the PFL function is unsufficuiently documented.

Too many components coming out of reset at the same time:

-- the FPGA (e.g. S4)

-- the CPLD itself

-- the related flash memory for the storage itself

So starting the whole procedure (a bit) later definitely helps.

I have also added LEDs and a pushbutton which would re-trigger a configuration, all is fine.

Have fun

Thouthi38