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Hi all,
I'm doing an DVB-ASI PCIE card. On this card, my FPGA receives DVB-ASI signal by using Altera ASI IP and converts it to parallel transport stream interface. The transport stream data are then sent to a PCIE bridge chip for PC decoding.
I found that the FPGA performance is different after each compilation. (No change to the RTL codes, IP, or timing constraints)
In some compilation results, the transport stream data can be successfully decoded and the video can be displayed. In other compilation results, the transport stream data cannot be decoded.
For those cases that the transport stream data cannot be decoded, I find that the transport stream data sent to PCIE bridge is incorrect.
I don't know what to do in order to make each compilation has good performance.
Should I add more constraints on my design or change my RTL code?
(My constraints now are some frequency constraints on clock, clock group constraints, and required constraints for Altera ASI IP)
I really don't have any idea now. Any suggestions are appreciated.
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can you simulate it functionally first. Possible causes:
io timing
fpga timing failure or timing passes but wrong constraints/deconstraints or wrong false paths
inadequate synchronisation across clock domains
buffers getting underflow/overflow
reset issues(check your simulation under different reset lengths.
any inputs being floating
...etc.
does failure/pass occur per build or per download powerup or per reset?
is it freeze sensitive? => timing
is it touch sensitive? => floating pins
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