Forum Discussion
Nathan_R_Intel
Contributor
6 years agoHie,
My apologies for the delayed response, as I missed your last questions.
Please check my replies:
Question:
What I don't get is, why then, in all the documentations for the Avalon Interface the 7 VCs are mentioned?
Answer:
The 7 VCs are only mentioned in the Address Map of Hard IP Configuration Space Registers. The address mapping of config space registers allocated memory space for optional features as well in the event the features are to be added in later revisions.
Question:
They always describe the "Address Map of Hard IP Configuration Space Registers", where VC0-VC7 is mentioned. Is there any way to access to this configuration space registers?
Answer:
As mentioned above, only the memory space is allocated. However, currently accessing the configuration space will not enable the VC feature as the equivalent arbitration logic is not available in the Hard IP.
Question:
Which Intel FPGAs/SoCs supports more than one TC (Traffic Class)?
Answer:
For now Arria V, Arria 10, Cyclone V, Cyclone 10, Stratix V and Stratix 10 devices support more than one TC.
Regards,
Nathan
- JDiet6 years ago
New Contributor
Thanks again Nathan!
Answer:
For now Arria V, Arria 10, Cyclone V, Cyclone 10, Stratix V and Stratix 10 devices support more than one TC.
=> Sorry but I forgot to ask before: Are these multiple TCs available for the outgoing traffic or only for the ingoing traffic or both?
Thanks in advance!
Julian