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Altera_Forum
Honored Contributor
15 years agooutput error
sir my following code gives null output: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity tskw is Port ( reset : in...
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Where do you see no output? For a behavioral simulation p is missing in the sensitivity list. --- Quote End --- So is K. All this circuit does is connect q to p when reset = '1'