Honored Contributor
Honored Contributor1 - Warnings concern me. Regardless though, you need to constrain the TX and RX interfaces between the FPGA and the PHY. These interfaces run at both 25MHz and 2.5MHz. In contstraining these interfaces, you'll need to constrain the clocks and data lines. You'll need to take into account the tsu, th, and tco timing parameters given for your PHY. You should ideally also take board trace length and skew into account but you may choose to ignore these if they are negligible.
Your ability to communicate with the PHY via the MDIO interface has no impact on the TX and RX interfaces. If there is a hardware problem with regards to the error you are receiving, it's either in the RX clock domain or in your system clock domain. BTW, how fast is your system clock? 2 - You are correct, I haven't provided the an SDC file. I am completely willing to explain the driver in depth to you. However, that is not the first place to look with regards to your problem. There is no point debugging the software until you are certain the hardware is rock solid. Jake
