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Altera_Forum
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16 years ago

OpenCores MAC driver error mesages

Hello! Im using a custom board with a KS8721BT chip. It have not any initialization so in the eth_ocm_phy_init() function i'm reseting it and waiting for auto negoriation to complete. Ap...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Correction, it doesn't set the error bit in the descriptor, it's just an interrupt to the processor.

Here is the associated Verilog: 

//Set Busy IRQ if a new frame comes in and
//we're too busy to receive it.
always @(posedge rxclk)     rx_bsy  <= rx_sop & rx_dv & ~rx_rdy;

In other words, if a new packet comes in and the Receive FIFO is full, you will get this error.

Jake