Ok I must be an idiot :P

Hello,

on the one hand, I see a lack of clarity with the Verilog always @ construct that requirers to use a posedge or negedge for an asynchronous reset. It's much clearer in VHDL to my opinion. But the basic point is that you can't have a synchronous register or a group of registers (e. g. a counter) with more than one clock input. If your design actually has two separate clocks, you must first preprocess these signals to get a single unequivocal clock and e. g. separate up and down qualifiers.

Regards,

Frank