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Altera_Forum
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14 years ago

Odd behavior when Master reads from two different data width memories!

Hi, I have an Avalon master with 256 bit data bus width which is interfaced to two slave memory components: 1. Memory 1 - 256 bit data bus width Avalon slave 2. Memory 2 - 32 bit data bu...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Well I did, and I do quite understand it very well .. but the problem here is why once the correct address is issued on avm0_address .. it slightly changes once it reaches the slave, observe that the same address reaches the slave but with +/- some value .. that's the address is close but not exact .. that's what confuses me :eek: