Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Odd behavior when Master reads from two different data width memories!

Hi, I have an Avalon master with 256 bit data bus width which is interfaced to two slave memory components: 1. Memory 1 - 256 bit data bus width Avalon slave 2. Memory 2 - 32 bit data bu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

refer to the avalon specification of the masters and slaves of different bus sizes, I guess u could find useful articles there. since the data bus width of ur master is bigger than the slave, it probably does read or write actions on consequtive addresses for a signle read/write istruction . This part of the avalon protocol is quite confusing!!I once had similar problems.