Noobe SDR SDRAM Question

Don't need to go far.

what is the efifo module in the verilog example used for? Looks like quite a bit of code just to control one SDRAM chip? (not that I know much about controlling these chips) :)

There are two designs. I have been using the older VHDL one, as I mentioned in the discussion. But the SOPC builder component should also work, probably without the Avalon FIFO.

Does SOPC builder work for free web edition? Is the IP free or does it create evaluation IP like the megafunctions that can only work while attached to Quartus environment?

SOPC builder itself uses an Opencore evaluation, I think, but this doesn't affect components, e. g. the SDRAM controller.

Tried SOPC builder - gives a warning the moment I set the data bits to 8. Also gives error and says that controller must be connected to an Avalon master???