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Altera_Forum
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15 years ago

No ouput for Modelsim DDR SDRAM Simulation

Dear all, In my modelsim simulation of DDR SDRAM write operation, I observed pulse in "local_write_request", "local_burstbegin", and changes in "local_address", "local_wdata", however, I didn'...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, I solved this problem.

It was a long time ago. From my memory, you need to set the simulation time very long, >80 us? and you see the DDR controller and memory activity after a long time, especially if you set calibration in the DDR controller, it will take a long time to do calibration or other process before memory access.

Hope it helps.

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I was wondering if you had solved your problem with Modelsim, and if so, what did you do to fix it. I seem to be experiencing a similar problem. I'm seeing local interface reponses but nothing between the DDR controller and memory.

Thanks.

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