NiosII DMA Tutorial

You understood correctly. That sequence is correct.

Anyway I don't know how to make the RD signal available outside the sopc system. You must expose the Avalon PIO read (or select) signal, so I think you probably need a modified version of the pio core. Maybe there's a way to export that signal, but I've never made something alike.

You can try this workaround: use a tristate bus with a fake sram component; discard address,wr and rd signals; connect data to your fifo and use cs signal to update fifo output.