NiosII Debugging + Dual Port RAM Problems

Hello,

I have a system with one SOPC component that contains a Dual Port RAM, with one side conneted to Nios, by Avalon, as a MMSlave. The other side is accessed by the peripheral specific logic. I tested my system for simultaneous access on both sides. When I run it with Nios in debug, it only works (it means, the peripheral side can read/write correctly) when debug is in pause. When is is freely running, the access by the logic fails. On the Nios side, everything is ok.

Running the same system without debug, booting from EPCS, both sides work properly. Does anyone has already get the same situation? Any ideas are welcome. I´m using EP3C5F256

Thanks,

Lucas