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Altera_Forum
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17 years ago

Nios II CPU with debug module not detected

Hi I am new to Altera's design flow, so please bear with me. I have a DE3 board from Terasic with the Stratix III EP3SL150F1152C2N FPGA. Using SOPC builder, I created a system containing a...
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Altera_Forum
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13 years ago

I had this problem couple of days ago, i just had to delete the .SOF file in the project's directory (quartus not the monitoring project). and then i've recompiled the quartus project to generate the file again. no problems occured with the second regenerated .SOF file. let me know if this helps