Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Nios II CPU with debug module not detected

Hi I am new to Altera's design flow, so please bear with me. I have a DE3 board from Terasic with the Stratix III EP3SL150F1152C2N FPGA. Using SOPC builder, I created a system containing a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

When you downloaded sof file to FPGA, ¿does a window with a cancel button appear saying: "opencore plus status:click cancel to stop using opencoreplus Ip Time remaining unlimited."? If it does, don cancel it.

--- Quote End ---

Hi'

I do also get the same error message with a dsp builder design which consists of two Avalon Memory Mapped Slave blocks. I did all the pins assignments and just dont know what to do next. The funny thing is when I use a simple SOPC design with the "hello_world.c" code, it works witout any problem on IDE.

So what could be the issue with the DSP builder design?

Please help...