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Altera_Forum
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17 years ago

Nios II CPU with debug module not detected

Hi I am new to Altera's design flow, so please bear with me. I have a DE3 board from Terasic with the Stratix III EP3SL150F1152C2N FPGA. Using SOPC builder, I created a system containing a...
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Altera_Forum
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17 years ago

When you downloaded sof file to FPGA, ¿does a window with a cancel button appear saying: "opencore plus status:click cancel to stop using opencoreplus Ip Time remaining unlimited."? If it does, don cancel it.