Honored Contributorwhat can be the maximum and minimum MIPS of NIOS II (MHZ/frequency) for the cyclone III and what is the criteria for selection while constructing SOPC builder system design?
Means there must be some limitations how much clock i can give to nios II or other peripherals,so what are they limitations based on? Advanced thanks. :)
Honored ContributorYou can find this data in Nios and peripheral documentation. Anyway the reported values are usually ideal limits that your system is not expected to reach in the real world.
For example fmax specification for Nios in CIII is 175MHz, if I remember correctly. But it's very hard to go far above 100MHz in a real application. The fmax you can use is also strongly dependent on % of fpga usage, number of devices connected to cpu bus and on your ability in setting timing constrains.
